Processor with multiple execution pipelines

ABSTRACT

An apparatus and method system and method for increasing performance in a processor or other instruction execution device while minimizing energy consumption. A processor includes a first execution pipeline and a second execution pipeline. The first execution pipeline includes a first decode unit and a first execution control unit coupled to the first decode unit. The first execution control unit is configured to control execution of all instructions executable by the processor. The second execution pipeline includes a second decode unit, and a second execution control unit coupled to the second decode unit. The second execution control unit is configured to control execution of a subset of the instructions executable via the first execution control unit.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 16/594,830, filed on Oct. 7, 2019, which is a continuation of U.S. patent application Ser. No. 14/554,709, filed on Nov. 26, 2014, now issued U.S. Pat. No. 10,437,596, each of which is incorporated herein by reference.

BACKGROUND

Processors and other instruction execution machines apply various techniques to increase performance. Pipelining is one technique employed to increase the performance of processing systems such as microprocessors. Pipelining divides the execution of an instruction (or operation) into a number of stages where each stage corresponds to one step in the execution of the instruction. As each stage completes processing of a given instruction, and processing of the given instruction passes to a subsequent stage, the stage becomes available to commence processing of the next instruction. Thus, pipelining increases the overall rate at which instructions can be executed by partitioning execution into a plurality steps that allow a new instruction to begin execution before execution of a previous instruction is complete. A processor that includes a single instruction pipeline can execute instructions at a rate approaching one instruction per cycle.

SUMMARY

An apparatus and method for increasing performance in a processor, or other instruction execution device, while minimizing energy consumption are disclosed herein. In one embodiment, a processor includes a first execution pipeline and a second execution pipeline. The first execution pipeline includes a first decode unit and a first execution control unit coupled to the first decode unit. The first execution control unit is configured to control execution of all instructions executable by the processor. The second execution pipeline includes a second decode unit, and a second execution control unit coupled to the second decode unit. The second execution control unit is configured to control execution of only a subset of the instructions executable via the first execution control unit.

In another embodiment, a method includes fetching an instruction to be executed by a processor. Whether the instruction is executable by a first execution control unit configured to execute only a subset of all instructions executable by the processor is determined. The instruction is directed to a second execution control unit configured to execute all instructions executable by the processor based on the first execution control unit not being configured to execute the instruction.

In a further embodiment, an instruction execution device includes a first execution pipeline and a second execution pipeline. The first execution pipeline includes a first execution control unit and a first decode unit. The first execution control unit is configured to control execution of all instructions executable by the device, and to apply all operand addressing modes supported by the device to access operands. The first decode unit is coupled to the first execution control unit, and is configured to decode all instructions executable by the device. The second execution pipeline includes a second execution control unit and a second decode unit. The second execution control unit is configured to control execution of only a subset of the instructions executable via the first execution control unit, and to apply only register and immediate addressing modes to access operands. The second decode unit is coupled to the second execution pipeline, and is configured to decode only the subset of the instructions.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:

FIG. 1 shows a block diagram of a processor in accordance with various embodiments;

FIGS. 2 and 3 show diagrams of instruction execution in pipelines of a processor in accordance with various embodiments;

FIGS. 4 and 5 show performance of conventional processors relative to a multi-pipeline processor in accordance with various embodiments; and

FIG. 6 shows a flow diagram for a method for executing instructions in a multi-pipeline device in accordance with various embodiments.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. The recitation “based on” is intended to mean “based at least in part on.” Therefore, if X is based on Y, X may be based on Y and any number of additional factors. The term “subset,” as used herein, means a “proper subset” that includes fewer than all the elements of a set from which the subset is derived.

DETAILED DESCRIPTION

The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.

Superscalar processors include multiple instruction pipelines operating in parallel in order to provide execution of more than one instruction per cycle. In a superscalar processor, the fetch unit can provide more than one instruction per cycle, multiple instruction decoders determine which instructions can be executed in parallel, and multiple execution pipelines operate in parallel using redundant execution units. However, a superscalar processor generally has a much higher gate count and energy consumption than a single-scalar processor, and in real-world applications the performance increase provided by a superscalar processor may be much less than the full capacity of the execution pipelines. Consequently, the energy consumed per task by a superscalar processor can be significantly higher than the energy consumed by a single-scalar processor executing the same tasks. Increased per task energy consumption is one reason that superscalar processors are rarely applied in embedded systems that are directed to low energy consumption applications, such as applications in which long battery life is important.

Embodiments of the present disclosure include multiple execution pipelines arranged to increase the rate of instruction execution relative to single-scalar processors, and to reduce energy consumption in comparison to conventional superscalar processors. While conventional superscalar processors include multiple instruction decoders, each capable of decoding the full instruction set of the superscalar processor, embodiments disclosed herein include a single decoder capable of decoding the full instruction set, and one or more additional decoders capable of decoding only a small subset of the full instruction set. Similarly, embodiments of the present disclosure include a single execution pipeline capable of executing the full instruction set, and one or more additional execution pipelines capable of executing only the small subset of the full instruction set. The small subset of instructions executable by the additional execution pipeline(s) includes instructions most frequently executed in practical applications.

FIG. 1 shows a block diagram of a processor 100 in accordance with various embodiments. The processor 100 includes a fetch unit 102, a dispatcher 104, a full execution control unit 110, a subset execution control unit 112, a register file 116, and execution units 118. The processor 100 may include various other components and subsystems that have been omitted from FIG. 1 in the interest of clarity. For example, embodiments of the processor 100 may include instruction and/or data caches, memory, communication devices, interrupt controllers, timers, clock circuitry, direct memory access controllers, and various other components and peripherals.

The fetch unit 102 retrieves instructions to be executed by the processor 110 from a storage device, such as a random access memory. The fetch unit 102 may include program counters that specify the location of instructions being retrieved, pre-fetching logic that retrieves and stores instructions for later execution, etc.

The dispatcher 104 assigns each instruction provided by the fetch unit 102 for execution to one of the multiple execution pipelines of the processor 100, where each execution pipeline includes a decode unit and an execution control unit. In the embodiment of FIG. 1, the processor 100 includes two execution pipelines. Other embodiments of the processor 100 may include more than two execution pipelines. The dispatcher 104 includes full decode unit 106 and subset decode unit 108. The decode units 106, 108 examine the instructions received from the fetch unit 104, and translate each instruction into controls suitable for operating the associated execution control units, processor registers, and other components of the processor 100 to perform operations that effectuate execution of the instructions.

The full decode unit 106 is capable of decoding all instructions (i.e., the full and complete instruction set) executable by the processor 100. The subset decode unit 108 is capable of decoding only a small subset of the instructions executable by the processor 100 (i.e., a small subset of the instructions decodable by the full decoder 106). For example, the subset decode unit 108 may be capable of decoding only the most frequently executed instructions or a selected ones of the most frequently executed instruction. Some embodiments of the subset decode unit 108 may be capable of decoding only instructions that apply relatively simple operand addressing (e.g., instructions applying only register or immediate addressing modes).

The dispatcher 104 includes dependency logic 120 that identifies dependencies (e.g., data dependencies) between instructions being executed, and causes the decode units 106, 108 to resolve dependencies identified by the dependency logic 120. For example, on identification of a dependency by the dependency logic 120, the decode unit decoding the instruction subject to the dependency may delay transfer of the instruction to the execution control unit until the dependency has been resolved.

Each decode unit 106, 108 passes decoded instructions to the corresponding execution control unit. Full decode unit 106 passes instructions to full execution control unit 110 for execution, and subset decode unit 108 passes instructions to subset execution control unit 112 for execution. The full execution control unit 110 is a capable of executing all instructions (i.e., the full and complete instruction set) executable by the processor 100. The subset execution control unit 112 is capable of executing only a small subset of the instructions executable by the processor 100 (i.e., a small subset of the instructions decodable by the full decoder 106). For example, the subset execution control unit 112 may be capable of executing only selected instructions that are most frequently executed by the processor 100. Some embodiments of the subset execution control unit 112 may be capable of executing only instructions that apply relatively simple operand addressing (e.g., instructions applying only register or immediate addressing modes).

The full execution control unit 110 may include multiple execution stages 114 to provide a high instruction execution rate over the entire instruction set. The subset execution control unit 112 may include fewer execution stages 114 than the full execution control unit 110. For example, only a single execution stage 114 may be provided via the subset execution control unit 112 to execute the small subset of instructions executable by the subset execution control unit 112.

In some embodiments of the processor 100, the full decode unit 106 and full execution control unit 110 may decode and execute instructions of a complex instruction set (i.e., CISC instructions) and instructions of a reduced instruction set (i.e., RISC instructions) executable by the processor 100, and the subset decode unit 108 and subset execution control unit 112 may decode and execute only the RISC instructions. In some embodiments of the processor 100, the subset decode unit 108 and subset execution control unit 112 may decode and execute only a subset of the RISC instructions executable by the processor 100. For example, the subset decode unit 108 and subset execution control unit 112 may decode and execute only RISC instructions that apply only the ALU 122 and/or that manipulate only operands stored in the register file 116 or provided in the instruction itself (i.e., apply only register or immediate addressing modes).

The execution units 118 include various function units (shift unit, multiply unit, etc.) applied by the execution control units 110, 112 to manipulate data and perform other operations needed for instruction execution. The full execution control unit 110 may have access to and apply any and all of the function units provided by the execution units 118. The subset execution control unit 112 may have access to and apply fewer function units of the execution units 118 than the full execution control unit 110. For example, the subset execution control unit 112 may access and apply only the arithmetic logic unit (ALU) 122 in some embodiments. Some embodiments of the execution units 118 may include more than one instance of a function unit to facilitate parallel instruction execution in the execution pipelines. For example, the execution units 118 may include more than one ALU 122 to allow parallel access to ALU 122 functionality by the full execution control unit 110 and the subset execution control unit 112.

The register file 116 includes registers that store operands for access and manipulation by the dispatcher 104, the full execution control unit 110, the subset execution control unit 112, and the execution units 118. The number and/or width of the registers included in the register file 116 may be different in different embodiments of the processor 100.

In practice, the performance gained by inclusion of the subset decoder 108 and the subset execution control unit 112 in the processor 100 can approach that provided by conventional superscalar implementations, by providing parallel execution of the most frequently encountered instructions, while substantially reducing energy consumption relative to conventional superscalar implementations. The circuitry added to the processor 100 to implement the subset decoder 108 and the subset execution control unit 112 is relatively small in comparison to the circuitry of the full decoder 106 and the full execution control unit 110. As a result, the energy consumed by the subset decoder 108 and the subset execution control unit 112 is relatively low in comparison to that consumed by the full decoder 106 and the full execution control unit 110.

FIGS. 2 and 3 show diagrams of instruction execution in the processor 100. In FIG. 2, the fetch unit 102 provides, in fetch cycle 202, instructions to be decoded and executed. The full decode unit 106 decodes a first instruction in decode cycle 204, and the subset decode unit 108 decodes a second instruction in decode cycle 206, which is in parallel with decode cycle 204. Execution of the decoded instructions proceeds in parallel with full execution control unit 110 executing the first instruction in execution cycle 208. The second instruction is executed in parallel by the subset execution control unit 112, which executes the second instruction in execution cycle 210. Execution of the second instruction completes in a single cycle, while execution of the first instruction requires multiple cycles.

FIG. 3 shows a multi-instruction execution sequence in the processor 100. In the execution sequence of FIG. 3, performance of the processor 100 is very similar to that achievable by a conventional superscalar architecture because the execution timing is constrained by data dependencies. Executing selected instructions via the limited decoding and execution capabilities of the subset decode unit 108 and the subset execution control unit 112 can reduce the energy consumed by execution of the instruction sequence with little or no reduction in performance.

Instructions 1 and 2 are executed in parallel as explained with regard to FIG. 2. Instructions 3 and 4 are fetched in cycle 2, but a dependency 304 between the instructions causes the dispatcher 104 to delay execution of instruction 4 for one cycle. Accordingly, instruction 4 is decoded in cycle 4 in parallel with execution of instruction 3. Execution of instructions 3 and 4 may be performed in either of the pipelines of processor 100 that provide suitable decoding and execution functionality. In some embodiments, execution by the subset decode unit 108 and subset execution control unit 112 may be selected to reduce energy consumption.

Instructions 5 and 6 are fetched in cycle 3. Decoding of instruction 5 is delayed until cycle 5 due to dependency 310. Instruction 5 is a complex instruction that requires multiple execution cycles in the full execution control unit 110 to complete. Instruction 6 is also a complex instruction that must be executed in the full execution pipeline. Therefore, decoding of instruction 6 is delayed until cycle 6. In the instruction sequence of FIG. 3, instruction 6 is the only instruction for which decoding and subsequent execution is delayed by the limited decoding and execution capabilities of the subset decode unit 108 and the subset execution control unit 112 when compared to execution by a conventional superscalar implementation.

Instructions 7 and 8 are fetched in cycle 4 and execution is delayed. Instruction 7 is decoded by the subset decode unit in cycle 6, and executed in the subset execution control unit in cycle 7. Instruction 8 is decoded by the subset decode unit 108 in cycle 7, and executed in the subset execution control unit 112 in cycle 8. In various embodiments, instruction 8 may be executed in either pipeline of the processor 100.

FIGS. 4 and 5 show performance of conventional processors relative to the processor 100. In FIG. 4, execution performance for a practical application exhibiting low instruction parallelism (e.g. due to a substantial number of instruction dependencies) is shown. Because of the low instruction parallelism, performance of the processor 100 and the conventional superscalar processor are only slightly better than that of the single-scalar processor. The energy consumption of the processor 100 is slightly higher than that of the single-scalar processor, and the energy consumption of the conventional superscalar processor is substantially higher that the single-scalar processor and the processor 100.

FIG. 5 shows performance for a practical application exhibiting high instruction parallelism. Performance of both the conventional superscalar processor and the processor 100 is significantly higher than that of the single-scalar processor, with the conventional superscalar processor performing slightly better than the processor 100. However, the energy consumption of the conventional superscalar processor is substantially higher than single-scalar processor, and the processor 100 consumes less energy that the single-scalar processor. Thus, as shown in FIGS. 4 and 5, the processor 100 can provide a substantial performance increase over a single-scalar processor while consuming much less energy than a conventional superscalar processor.

FIG. 6 shows a flow diagram for a method 600 for executing instructions in accordance with various embodiments. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some embodiments may perform only some of the actions shown.

In block 602, the fetch unit 102 fetches instructions from memory for execution and provides the fetched instructions to the dispatcher 104.

In block 604, the dispatcher 104 evaluates an instruction received from the fetch unit 102, and determines whether the instruction can be executed by the subset execution pipeline (e.g., the subset decoder 108 and subset execution control unit 112). As explained above, the subset execution pipeline executes only a small subset of the full instruction set executable by the processor 100. For example, the subset execution pipeline may execute only RISC instructions or a subset of the RISC instructions executable by the processor 100, while the full instruction pipeline can execute any and all instructions (including CISC instructions) executable by the processor 100.

If, in block 606, the subset execution pipeline is deemed capable of executing the instruction evaluated by the dispatcher 104, then in block 608, the dispatcher 104 routes the instruction to the subset decoder 108. The subset decoder 108 decodes the instruction.

In block 610, the subset decoder 108 passes the decoded instruction to the subset execution control unit 112, and the subset execution control unit 112 applies the execution units 118 to execute the instruction. In some embodiments, the subset execution control unit 112 executes the instruction in a single cycle.

If, in block 606, the subset execution pipeline is deemed incapable of executing the instruction evaluated by the dispatcher 104, then in block 612, the dispatcher 104 routes the instruction to the full decoder 106. The full decoder 106 decodes the instruction.

In block 614, the full decoder 106 passes the decoded instruction to the full execution control unit 110, and the full execution control unit 110 applies the execution units 118 to execute the instruction. In some embodiments, the full execution control unit 110 executes the instruction in a multiple cycles.

While embodiments of the present disclosure have been described with reference to the processor 100, embodiments of the multi-pipeline arrangement disclosed herein may be applied to improve performance while minimizing energy consumption in a wide variety of instruction execution devices.

The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications. 

What is claimed is:
 1. A processing device comprising: an instruction fetch unit; a first decode unit coupled to the instruction fetch unit; a first execution control unit coupled to the first decode unit; a second decode unit coupled to the instruction fetch unit; a second execution control unit coupled to the second decode unit; and a set of execution units coupled to the first execution control unit and the second execution control unit wherein: the first decode unit and the first execution control unit are configured to cause the set of execution units to execute any instruction of a first instruction set; and the second decode unit and the second execution control unit are configured to cause the set of execution units to execute any instruction of a second instruction set that is a subset of the first instruction set such that a remainder of the first instruction set is not in the second instruction set.
 2. The processing device of claim 1 further comprising a register file coupled to the set of execution units, wherein each instruction in the second instruction set utilizes a register operand mode, an immediate addressing mode, or a combination thereof.
 3. The processing device of claim 1, wherein the second instruction set includes only reduced instruction set computer (RISC) instructions and the remainder of the first instruction set includes complex instruction set computer (CISC) instructions.
 4. The processing device of claim 1, wherein the second instruction set includes only instructions that can be executed in one clock cycle and the remainder of the first instruction set includes instructions that are executed in more than one clock cycle.
 5. The processing device of claim 1, wherein: the set of execution units includes an arithmetic logic unit and a remainder of the set of execution units; the first execution control unit and the second execution control unit are each configured to control the arithmetic logic unit; the first execution control unit is configured to control the remainder of the set of execution units; and the second execution control unit is not configured to control the remainder of the set of execution units.
 6. The processing device of claim 5, wherein the remainder of the set of execution units includes at least one of: a shift unit, a multiply unit, a floating point unit, or a load/store unit.
 7. The processing device of claim 1, wherein: the first execution control unit is configured to cause the set of execution units to execute an instruction of the first instruction set in a first number of pipeline stages; and the second execution control unit is configured to cause the set of execution units to execute an instruction of the second instruction set in a second number of pipeline stages that is less than the first number of pipeline stages.
 8. The processing device of claim 1, wherein: the instruction fetch unit is configured to receive a first instruction and provide the first instruction to either the first execution control unit or the second execution control unit based on whether the first instruction is in the second instruction set.
 9. The processing device of claim 1, wherein the first decode unit and the second decode unit are coupled to operate in parallel.
 10. The processing device of claim 8, wherein the first execution control unit is configured to cause the set of execution units to execute a first instruction and the second execution control unit is configured to cause the set of execution units to execute a second instruction in parallel with the first instruction.
 11. A processing device comprising: a first decode unit; a second decode unit coupled in parallel with the first decode unit; a first execution control unit coupled to the first decode unit; a second execution control unit coupled to the second decode unit; and a set of execution units coupled to the first execution control unit and the second execution control unit wherein: the first decode unit and the first execution control unit are configured to cause the set of execution units to execute a first instruction having a first addressing mode and a second instruction having a second addressing mode that is different from the first addressing mode; and the second decode unit and the second execution control unit are configured to cause the set of execution units to execute the first instruction having the first addressing mode and not configured to cause the set of execution units to execute the second instruction having the second addressing mode.
 12. The processing device of claim 11, wherein the first addressing mode includes at least one of a register operand mode or an immediate addressing mode.
 13. The processing device of claim 11, wherein the first instruction utilizes only a register operand mode, an immediate addressing mode, or a combination thereof.
 14. The processing device of claim 11, wherein the second addressing mode is not a register operand mode or an immediate addressing mode.
 15. The processing device of claim 11, wherein: the first execution control unit includes a first number of execution stage circuits; and the second execution control unit includes a second number of execution stage circuits that is less than the first number of execution stage circuits.
 16. The processing device of claim 15, wherein: the second decode unit and the second execution control unit are configured to cause the set of execution units to execute the first instruction in a single clock cycle; and the first decode unit and the first execution control unit are configured to cause the set of execution units to execute the second instruction in more than one clock cycle.
 17. The processing device of claim 13, wherein: the set of execution units includes an arithmetic logic unit and a remainder of the set of execution units; the first execution control unit and the second execution control unit are each configured to control the arithmetic logic unit; and the first execution control unit but not the second execution control unit is configured to control the remainder of the set of execution units.
 18. The processing device of claim 17, wherein the remainder of the set of execution units includes at least one of: a shift unit, a multiply unit, a floating point unit, or a load/store unit.
 19. The processing device of claim 11 further comprising an instruction fetch unit, wherein the first decode unit and the second decode unit are coupled to the instruction fetch unit in parallel.
 20. The processing device of claim 19, wherein the first execution control unit and the second execution control unit are configured to cause the set of execution units to execute instructions in parallel. 